The method of using Altera CPLD EPM3064 is as follows, and refer to my teacher's book.
Schmitt trigger circuit should be added to the input of cpld is as follows.
Construction drawings (look up from the bottom of the IC)
Timing diagram
The code is as follows
library ieee ;
use ieee.std_logic_1164.all ;
use ieee.std_logic_unsigned.all ;
use ieee.std_logic_arith.all ;
--*******************************
entity coding is
port ( ASCII_IN : in std_logic_vector(7 downto 0) ;
TG,ACK,STOP,START,MOD9,HLBITE: in std_logic ;
Y : out std_logic_vector(7 downto 0));
end coding ;
--*******************************
architecture A_if_then_else of coding is
begin
process (TG,ACK,STOP,START,MOD9,HLBITE,ASCII_IN)
begin
if tg'EVENT and tg='1' then
if STOP='1' then
if START='1' then Y <= "01111100" ;
else Y<="01111000";
end if;
elsif HLBITE='1' then Y <= ASCII_IN ;
elsif MOD9='1' and ACK='1' then Y <= "10000000" ;
elsif MOD9='1' and ACK='0' then Y<="01111110";
else Y <= "11111111" ;
end if;
end if;
end process;
end A_if_then_else ;
library ieee ;
use ieee.std_logic_1164.all ;
use ieee.std_logic_unsigned.all ;
use ieee.std_logic_arith.all ;
--*******************************
entity hx2ac is
port ( HX :std_logic_vector(3 downto 0) ;
Y : out std_logic_vector(7 downto 0)) ;
end hx2ac ;
--*******************************
architecture A_with_select_when of hx2ac is
signal Temp : std_logic_vector(3 downto 0) ;
begin
Temp <= HX;
with Temp select
Y <= "01100000" when "0000" ,
"01100010" when "0001" ,
"01100100" when "0010" ,
"01100110" when "0011" ,
"01101000" when "0100" ,
"01101010" when "0101" ,
"01101100" when "0110" ,
"01101110" when "0111" ,
"01110000" when "1000" ,
"01110010" when "1001" ,
"10000010" when "1010" ,
"10000100" when "1011" ,
"10000110" when "1100" ,
"10001000" when "1101" ,
"10001010" when "1110" ,
"10001100" when "1111" ,
"11111111" when others ;
end A_with_select_when ;
library ieee ;
use ieee.std_logic_1164.all ;
use ieee.std_logic_unsigned.all ;
use ieee.std_logic_arith.all ;
--*******************************
entity MD24D is
port ( CK : in std_logic ;
CK232,M8,M16 :OUT std_logic);
end md24D ;
--*******************************
architecture A_generic of mD24D is
begin
process(CK)
VARIABLE Q_temp: std_logic_vector(4 DOWNto 0);
begin
if CK'event and CK='1' then
if Q_temp="10111" then Q_temp:="00000";
ELSE Q_temp:= Q_temp + 1;
end if;
end if ;
CK232 <= Q_TEMP(4);
M8 <= Q_TEMP(2);
M16 <= Q_TEMP(3);
end process ;
end A_generic ;
library ieee ;
use ieee.std_logic_1164.all ;
use ieee.std_logic_unsigned.all ;
use ieee.std_logic_arith.all ;
--*******************************
entity shift8ct is
port ( DATA,CK,CLR : in std_logic ;
Q : out std_logic_vector(3 downto 0);
AT4,AT8,AT9,AK: out std_logic) ;
end shift8ct ;
--*******************************
architecture A_generic of shift8ct is
signal Q_temp : std_logic_vector(0 to 9) ;
begin
process(DATA,CK,CLR)
variable s_temp,r_temp : std_logic_vector(0 to 3) ;
begin
if CLR='0' then Q_temp <= "0000000000" ;r_temp := "0000" ;S_temp := "0000" ;
elsif CK'event and CK='1' then
r_temp := r_temp + 1 ;
Q_temp(0)<= DATA;
for i in 0 to 8 loop
Q_temp(i+1)<= Q_temp(i) ;
end loop ;
if r_temp="0100" then s_temp:="1000";
elsif r_temp="1000" then s_temp:="0100";
elsif r_temp="1001" then s_temp(0):='0';s_temp(1):='0';s_temp(2):='1';s_temp(3):=data;
elsif r_temp="1010" then r_temp := "0001" ;s_temp:="0000";
else s_temp:="0000";
end if;
end if ;
AT4<=s_temp(0);AT8<=s_temp(1);AT9<=s_temp(2);AK<=s_temp(3);
end process ;
Q <= Q_temp(0 to 3) ;
end A_generic ;
library ieee ;
use ieee.std_logic_1164.all ;
use ieee.std_logic_unsigned.all ;
use ieee.std_logic_arith.all ;
--*******************************
entity shut is
port ( RXP : in std_logic_vector(7 downto 0);
CK,LOAD : in std_logic ;
TX : out std_logic);
end shut ;
--*******************************
architecture A_generic of shut is
signal Q_temp : std_logic_vector(8 downto 0) ;
begin
process(RXP,LOAD,CK)
begin
if LOAD='1' then
q_temp <= (RXP & '1') ;
elsif CK'event and CK='1' then
Q_temp(8)<='1';
for i in 8 downto 1 loop
Q_temp(i-1)<= Q_temp(i) ;
end loop ;
end if;
end process ;
TX <= Q_temp(0) ;
end A_generic ;
library ieee ;
use ieee.std_logic_1164.all ;
use ieee.std_logic_unsigned.all ;
use ieee.std_logic_arith.all ;
--*******************************
entity FILTER is
port ( D,CLK : in std_logic ;
Q : out std_logic ) ;
end FILTER ;
--*******************************
architecture A_table of FILTER is
signal Q_temp : std_logic ;
begin
process(D,CLK)
begin
if CLK'event and CLK='1' then
Q_temp <=D;
end if;
end process ;
end A_table;
library ieee ;
use ieee.std_logic_1164.all ;
use ieee.std_logic_unsigned.all ;
use ieee.std_logic_arith.all ;
--*******************************
entity STOPS is
port ( SDA,SCL : in std_logic ;
Q : out std_logic ) ;
end STOPS ;
--*******************************
architecture A_table of STOPS is
signal Q_temp : std_logic ;
begin
process(SDA,SCL)
begin
if SCL='0' then
Q_temp <= '0' ;
elsif SDA'event and SDA='1' then
Q_temp <='1';
end if;
Q <= Q_temp ;
end process ;
end A_table;
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